Up-down voltage converter circuit and method

ABSTRACT

An integrated voltage converter ( 104 ) includes a first switch (S 1 ) that turns on with a value of a control signal (UP/DOWN) to generate a coil current (I COIL ) at a node ( 208 ) when an output voltage (V OUT ) of the voltage converter is greater than a reference voltage (V BATT −ΔV). A second switch (S 2 ) coupled to the node turns on with another value of the control signal to generate the coil current when the output voltage is less than the reference voltage. The coil current discharges through the second switch to an output ( 202 ) of the voltage converter to develop the output voltage.

BACKGROUND OF THE INVENTION

[0001] The present invention relates in general to integrated circuitsand, more particularly, to up-down voltage converters integrated on asemiconductor substrate.

[0002] Many applications use voltage converters to convert an inputvoltage at one value to either a higher or lower valued output voltageas needed by a load circuit. For example, portable smart card readerstypically use a battery to supply a typical input voltage of about 3.6volts. A voltage converter in the card reader uses the battery voltageto generate a transformer or coil current that is used to develop anoutput voltage at either three volts or five volts, depending on thetype of smart card which is inserted into the reader. Most smart cardreaders maintain a low fabrication cost by using a single up-downvoltage converter to step the battery voltage to five volts or down tothree volts as needed.

[0003] Previous up-down voltage converters use a four transistor bridgearrangement to switch the coil current to develop the output voltage.However, this arrangement routes the coil current serially through twoof the transistors, which results in power being dissipated by theresistance of two conducting transistors. To avoid an excessive powerloss, larger transistors with lower resistances are used, but the largetransistors occupy a large die area, which therefore increases the costof manufacturing the voltage converters.

[0004] Hence, there is a need for an up-down voltage converter andmethod of converting a voltage that uses fewer transistors in order toreduce the cost and increase the power efficiency of the voltageconverter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is a block diagram of a portable smart card reader using avoltage converter to generate an output voltage;

[0006]FIG. 2 is a schematic diagram showing further detail of thevoltage converter;

[0007]FIG. 3 is a timing diagram showing a waveform of the coil currentgenerated by the voltage converter; and

[0008]FIG. 4 is a schematic diagram showing the voltage converter in analternate embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

[0009] In the figures, elements having the same reference number havesimilar functionality.

[0010]FIG. 1 is a schematic diagram of a portable smart card reader 10operating with a load 106 that includes an inserted smart card,including a battery 102 and a direct current (DC) to DC voltageconverter 104. In one embodiment, battery 102 provides a battery supplyvoltage V_(BATT) operating at a voltage of about 3.6 volts.

[0011] DC to DC converter 104 converts battery supply voltage V_(BATT)received at an input node 200 to an output supply voltage V_(OUT) at anoutput node 202. The circuitry designated as load 106 includes a smartcard that may be either of two types, i.e., a three volt smart card or afive volt smart card, referring to the supply voltage specified foroperating each type of smart card. The type of smart card is detected bysystem 10 and the corresponding value of VOUT is provided by converter104. Hence, if a three volt smart card is inserted, converter 104operates in a step down mode to convert V_(BATT)=3.6 volts to a loweroutput supply voltage V_(OUT)=3.0 volts. If a five volt smart card isinserted, converter 104 operates in a step up mode to convertV_(BATT)=3.6 volts to a higher output supply voltage V_(OUT)=5.0 volts.

[0012]FIG. 2 is a schematic diagram showing DC to DC converter 104 infurther detail, including an inductor or coil L₁, a capacitor C₁,transistor switches S₁ and S₂, comparators 220, 230 and 246, currentsources 242 and 244, logic blocks 221 and 250 and resistors 251 and 252.Battery supply voltage V_(BATT) is received at node 200 and outputsupply voltage V_(OUT) is produced at node 202 to have a value of either3.0 volts or 5.0 volts, depending on the type of smart card. V_(OUT)supplies a load current I_(LOAD) of about fifty milliamperes to operatea smart card included in load 106. Except for coil L₁ and capacitor C₁,the components shown in FIG. 2 are formed on a single semiconductor dieas an integrated circuit. In one embodiment, coil L₁ has a value ofabout twenty-two microhenries and capacitor C₁ has a value of about tenmicrofarads.

[0013] Switch S₁ is a standard high current n-channel metal oxidesemiconductor field effect transistor (MOSFET) configured to switch acoil current I_(COIL) through coil L₁ at a level of at least one hundredfifty milliamperes. Switch S₂ is a standard high current p-channelMOSFET also capable of supplying coil current I_(COIL) at a level of atleast one hundred fifty milliamperes.

[0014] Comparator 220 monitors output supply voltage V_(OUT) forcomparing with a reference voltage V_(REF) to provide voltageregulation. A digital enabling signal EN is produced on a node 223 witha logic high value to activate switch S₁ and/or switch S₂ through logicblocks 221 and 250 when V_(OUT) is below its predetermined regulationvalue of either three or five volts. Comparator 220 is referred to as ahysteretic comparator since its inputs typically are configured to haveabout tone hundred millivolts of hysteresis to avoid excessive switchingwhen V_(OUT) is near its target regulation value.

[0015] Logic block 221 has an input at a node 225 for receiving anON/OFF enabling signal that activates DC to DC converter 104 when asmart card is inserted in the reader. When no smart card is present,ON/OFF initiates a standby mode which deactivates portions of converter104 to reduce standby power consumption. Hence, ON/OFF has the effect ofdisabling switches S₁ and S₂ during the standby mode. An output providesan enabling signal ENABLE on a node 262.

[0016] Comparator 230 compares output supply voltage V_(OUT) with areference voltage (V_(BATT)−ΔV) to determine whether converter 104 isoperating in an up- or down-conversion mode. The advantages of settingthe reference at a few hundred millivolts below V_(BATT) is described indetail below. In one embodiment, ΔV has a value of about two hundredmillivolts. The comparison produces a digital mode signal UP/DOWN on anode 232.

[0017] Current sources 242 and 244 supply reference currents I_(REF1)and I_(REF2), respectively, that flow through resistor 252 to batterysupply voltage V_(BATT) and establish a reference potential V₂₀₇ on anode 207.

[0018] Resistors 251-252 are matched or scaled to provide resistancesR₂₅₁ and R₂₅₂, respectively, in a ratio that is constant over aspecified range of operating, processing and environmental conditions.In one embodiment, R₂₅₁ is about two ohms and R₂₅₂ is about two kilohmsto provide a resistance ratio R₂₅₂/R₂₅₁ of about 1000:1.

[0019] Comparator 246, in combination with resistors 251-252, currentsources 242 and 244 and a switch 245, essentially functions as a currentsensor 239. An input coupled to a node 206 receives a voltage V₂₀₆resulting from the flow of coil current I_(COIL) through resistor 251.Another input receives reference potential V₂₀₇ for comparing withvoltage V₂₀₆ to produce a digital phase signal CHG/DSCHG at an output ona node 249 to control whether coil current I_(COIL) is charging ordischarging, i.e., increasing or decreasing. When I_(COIL) is charging,CHG/DSCHG is logic high to close switch 245 so thatV₂₀₇=V_(CHG)=V_(BATT)−R₂₅₂*(I_(REF1)+I_(REF2)). When I_(COIL) isdischarging, CHG/DSCHG is logic low to open switch 245 so thatV₂₀₇=V_(DSCHG)=V_(BATT)−R₂₅₂*I_(REF1). In effect, V_(CHG) functions toset a maximum or upper current I_(PEAK)=(R₂₅₂/R₂₅₁)*(I_(REF1)+I_(REF2))for I_(COIL), while V_(DSCHG) functions to set a minimum or lowercurrent limit I_(VALLEY)=(R₂₅₂/R₂₅₁)*I_(REF1) for I_(COIL).

[0020] Logic block 250 includes a combinational logic circuit whoseinputs receive ENABLE, UP/DOWN and CHG/DSCHG as control signals andwhose outputs at nodes 256 and 254 produce drive signals VS1 and VS2 fordriving the gates of switches S₁ and S₂, respectively. A truth table forlogic block 250 is shown in Table I below, where H indicates a logichigh level, L indicated a logic low, and X indicates a “don't care”state, i.e., either H or L. Note that logic block 250 includes levelshifting circuitry to provide logic high values for VS1 and VS2 at thepotential of either V_(BATT) or V_(OUT), as described in detail below.Logic low operates at ground potential. TABLE I CHG/ STATE UP/DOWN DSCHGENABLE VS2 VS1 I L H H L L II L L H H (V_(BATT)) L III L X L H(V_(BATT)) L IV H H H H (V_(OUT)) H (V_(OUT)) V H L H L L VI H X L H(V_(OUT)) L

[0021] The detailed operation of converter 104 can be understood byreferring to FIG. 3, which shows a waveform of coil current I_(COIL)versus time over several cycles of operation. First, the down conversionmode is described as follows, assuming that V_(BATT)=3.6 volts andV_(OUT)=3.0 volts.

[0022] Assume further that initially, at time T0, output supply voltageV_(OUT) is zero and coil current I_(COIL) is zero. The logic values forENABLE, UP/DOWN and CHG/DSCHG are represented in Table 1 as state I.CGH/DSCHG is logic high to close switch 245 to sum reference currentsI_(REF1) and I_(REF2) at node 207. VS1 is logic low so switch S₁ is off.VS2 is low, so switch S₂ is turned on to form a conduction path betweena node 208 and output node 202. The initial voltage across coil L₁ is(V_(BATT)−V_(OUT)), which is nearly equal to V_(BATT). Coil currentI_(COIL) increases with time to charge or store magnetic energy in coilL₁, and is routed through S₂ to output node 202. This period whenI_(COIL) is charging or increasing is designated as the charging phaseof operation. Hence, during the charging phase, I_(COIL) flows tocapacitor C₁ to begin to develop output supply voltage V_(OUT). Fortypical values of C₁, V_(OUT) increases a few hundred millivolts duringthe first cycle.

[0023] At time T1, I_(COIL) increases to its maximum limit valueI_(PEAK), which causes comparator 246 to switch CHG/DSCHG to a logic lowvalue as shown in state II of Table I. In one embodiment, I_(PEAK) has avalue of about one hundred fifty milliamperes. Switch 245 is opened soonly reference current I_(REF1) flows through resistor 252, settingpotential V₂₀₇ to a value representative of minimum current levelI_(VALLEY). VS2 is set to a logic high value of V_(BATT), which allowsthe potential of node 208 to rise until switch S₂ turns on to dischargeI_(COIL) into capacitor C₁ to further develop the potential of V_(OUT).This period during which I_(COIL) is decaying or decreasing isdesignated as the discharging phase of I_(COIL).

[0024] At time T2, I_(COIL) decays to a value equal to I_(VALLEY),causing comparator 246 to produce CHG/DSCHG with a logic high value andVS2 with a logic low value to begin another cycle indicated in Table Ias state I. Note that switch S₁ remains off during both the charging anddischarging phases of the above described cycle. Note further thatswitch S₂ routes I_(COIL) to charge capacitor C₁ during both thecharging and discharging phases of I_(COIL), i.e., when I_(COIL) is bothincreasing and decaying. This scheme allows V_(OUT) to be developed infewer cycles and, by switching I_(COIL) only through a single device S₂,converter 104 functions with a low parts count and fabrication cost aswell as a high power efficiency. The period from T0 to T2 to completeone cycle typically ranges from about two to ten microseconds, or afrequency between one hundred kilohertz and five hundred kilohertz. Itis considered desirable to maintain the period within this time range inorder to control electromagnetic interference and to maintain tighterregulation of V_(OUT).

[0025] When converter 104 is operating as described above as a step downvoltage converter in which the target value of V_(OUT) is less thanV_(BATT), the cycles continue to alternate between state I and state IIas described until capacitor C₁ has accumulated sufficient charge fromI_(COIL) to reach the V_(OUT) target value of 3.0 volts. At that point,logic block 221 generates a logic low level for ENABLE, which switchesVS2 to a logic high V_(BATT) potential, allowing I_(COIL) to decay tozero and deactivating switches S₁ and S₂. This idle condition is shownin Table I as state III. Converter 104 remains in this idle state untilV_(OUT) decays by the amount of hysteresis in comparator 220, whenENABLE is again set logic high to begin a new cycle.

[0026] Now assume converter 104 is operating in a step up converter modein which 5.0 volts is the target value of V_(OUT) which is higher thanV_(BATT)=3.6 volts. ENABLE is high and operation proceeds as describedabove until V_(OUT) is within ΔV volts of V_(BATT). At this point, theswitching frequency of converter 104 decreases to about one hundredkilohertz because of the low potential (V_(BATT)−V_(OUT)) across coilL₁. As V_(OUT) reaches the value of reference voltage (V_(BATT)−ΔV) ,comparator 230 produces UP/DOWN with a logic high value to switch theoperation to the step up or up conversion mode shown as state IV inTable I. In one embodiment, ΔV has a value of about two hundredmillivolts, so when V_(BATT)=3.6 volts, reference voltage(V_(BATT)−ΔV)=3.4 volts approximately. The operation proceeds asfollows.

[0027] The charging phase, when I_(COIL) is increasing, occurs bysetting VS1 to a logic high to turn on switch S1. This mode of operationallows I_(COIL) to increase more rapidly because the voltage across coilL₁ is essentially V_(OUT), rather than V_(OUT)−V_(BATT). This techniquemaintains the operating frequency of converter 104 above at least onehundred kilohertz. I_(COIL) increases until reaching the value ofI_(PEAK), at which time comparator 246 generates CHG/DSCH with a logiclow, VS1 undergoes a high to low transition to turn off S₁, and VS2 ismade logic low, turning on switch S₂ to discharge I_(COIL) intocapacitor C₁, as shown as state V in Table I. When I_(COIL) decays tothe value of I_(VALLEY), converter 104 returns to state IV of Table I.Converter 104 alternates between states IV and V until V_(OUT) increasesto its target value, at which point logic block 221 generates ENABLEwith a logic low to put converter 104 in an idle state designated asstate VI in Table I.

[0028]FIG. 4 is a schematic diagram showing DC to DC converter 104 in analternate embodiment incorporating an analog type regulation of V_(OUT),rather than the hysteretic regulation of the embodiment shown in FIG. 2.The structure and operation of most of the devices are similar to whathas been described, except for the addition of an error amplifier 247and the function of current sources 242 and 244.

[0029] Error amplifier 247 is a standard analog amplifier formed in theregulation feedback path to produce an analog error signal V_(ERR) on anode 222 as a difference between output supply voltage V_(OUT) andreference voltage V_(REF). V_(ERR) is coupled to an input of comparator220 for comparing with a skip threshold voltage V_(SKIP) to producedigital enabling signal EN, which functions as described above. WhenV_(ERR) is larger than V_(SKIP), i.e., when converter 104 is essentiallyout of regulation, EN is logic high. However, in order to avoidexcessive switching when V_(OUT) is at or near its target value, whenV_(ERR) is less than V_(SKIP), EN is made logic low to put converter 104in an idle state, either state III or state VI. In effect, V_(SKIP) setsa regulation limit within which converter 104 is idled. In oneembodiment, V_(SKIP) has a value of about fifty millivolts, which meansconverter 104 regulates to within fifty millivolts of its target value.

[0030] As a feature of this embodiment, as V_(OUT) approaches its targetvalue, the limit currents I_(PEAK) and I_(VALLEY) have values which areadjusted in an analog fashion by V_(ERR). Hence, as V_(OUT) approachesits target value, I_(PEAK) and I_(VALLEY) are reduced accordingly toallow smaller corrections to be made to V_(OUT) while maintainingoperation over a narrower frequency range. In one embodiment, I_(REF1)has an adjustment range between about ten and about one hundredmicroamperes, and I_(REF2) is adjustable from about twenty to about twohundred microamperes.

[0031] In summary, the present invention provides a voltage convertercircuit and method of converting a voltage that has a high performanceand a low manufacturing cost. A first transistor is switched on by afirst value of a control signal to generate a coil current at a nodewhen the converter's output voltage is greater than a reference voltage.A second switch is turned on by a second value of the control signal togenerate the coil current when the output voltage is less than thereference voltage. The second switch is coupled between the node and theoutput of the converter circuit to discharge the coil current to developthe output voltage with either value of the control signal. Theconverter adjusts to either a step up or step down conversion modeautomatically while using only two high current switching transistorsthat can be integrated on the same semiconductor die with controlcircuitry using a standard CMOS process. Since the coil current isrouted through only one switching transistor at a time, the voltageconverter has a low switching resistance and a high power efficiency.Moreover, by using only two switching transistors to charge anddischarge the coil current for up or down conversion, the voltageconverter occupies a small die area and consequently has a lowfabrication cost. While regulating, the coil current fluctuates betweenupper and lower current limits, and therefore decays to zero only undera no load or idling condition. By operating with a nonzero coil current,a high switching efficiency is achieved while reducing coil ringingduring switching to maintain a low level of electromagneticinterference. In addition, the benefits of the invention are obtained byusing an inductor or coil, rather than a more expensive transformer,which further reduces the fabrication cost of a system.

What is claimed is:
 1. An integrated converter circuit, comprising: afirst switch that turns on with a first value of a control signal togenerate a coil current at a node when an output voltage of theintegrated converter circuit is greater than a first reference voltage;and a second switch coupled to the node and turning on with a secondvalue of the control signal to generate the coil current when the outputvoltage is less than the first reference voltage, wherein the coilcurrent is discharged through the second switch to an output of theintegrated converter circuit to develop the output voltage.
 2. Theintegrated converter circuit of claim 1, further comprising a firstcomparator having a first input for sensing the output voltage, a secondinput receiving the first reference voltage and an output for providingthe control signal.
 3. The integrated converter circuit of claim 2,further comprising a second comparator having a first input for sensingthe output voltage, a second input receiving a second reference voltageand an output coupled for enabling the first and second switches.
 4. Theintegrated converter circuit of claim 1, wherein the first switchcomprises an n-channel metal oxide semiconductor field effect transistorand the second switch comprises a p-channel metal oxide semiconductorfield effect transistor.
 5. The integrated converter circuit of claim 4,wherein a load current of the integrated converter circuit is at leastfifty milliamperes.
 6. The integrated converter circuit of claim 1,further comprising: a first current source providing a first current toset a minimum value to which the coil current decays; and a secondcurrent source operating in response to a switching signal for providinga second current that is summed with the first current to establish amaximum value to which the coil current increases.
 7. The integratedconverter circuit of claim 6, further comprising a comparator having afirst input for sensing the coil current, a second input coupled forsensing the first and second currents and an output for providing theswitching signal for enabling the second current source.
 8. A voltageconverter, comprising: a first comparator for comparing an output signalof the voltage converter with a first reference signal to produce afirst control signal; a first transistor coupled for charging a coilcurrent with the first control signal when the output signal is greaterthan the first reference signal; and a second transistor coupled fordischarging the coil current to an output of the voltage converter todevelop the output signal, wherein the second transistor responds to thefirst control signal by charging the coil current when the output signalis less than the first reference signal.
 9. The voltage converter ofclaim 8, wherein the coil current is discharged to a minimum valueindicative of a first current, further comprising a first current sourcefor supplying the first current to a node.
 10. The voltage converter ofclaim 9, wherein the coil current is charged to a maximum valueindicative of a second current, further comprising a second currentsource for supplying a second current to the node.
 11. The voltageconverter of claim 10, further comprising a second comparator having afirst input coupled for sensing the coil current, a second input coupledto the node and an output for providing a switching signal that routesthe second current to the node when the coil current is charging. 12.The voltage converter of claim 10, further comprising a secondcomparator that compares the output signal to a second reference signalto produce an adjustment signal for modifying levels of the first andsecond currents.
 13. The voltage converter of claim 12, furthercomprising a third comparator having a first input for receiving theadjustment signal, a second input for receiving a third reference signaland an output for providing a second control signal for deactivating thefirst and second transistors.
 14. A method of converting a supplyvoltage to an output voltage, comprising the steps of: generating a coilcurrent through a first conduction path coupled to a first node when theoutput voltage is greater than a first reference voltage; generating thecoil current through a second conduction path coupled between the firstnode and a second node to develop the output voltage at the second nodewhen the output voltage is less than the first reference voltage; andenabling the second conduction path when the coil current increases to afirst limit value to discharge the coil current to the second node. 15.The method of claim 14, wherein the step of generating the coil currentthrough a second conduction path includes the step of activating thesecond conduction path with a first value of a control signal, and thestep of enabling includes the step of activating the second conductionpath with a second value of the control signal.
 16. The method of claim15, further comprising the step of comparing the coil current to a firstreference current indicative of the first limit value to generate thecontrol signal.
 17. The method of claim 14, further comprising the stepof comparing the output voltage to a second reference voltage todeactivate the first and second conduction paths when the output voltageis within a predetermined potential of the second reference voltage. 18.The method of claim 14, wherein the step of generating the coil currentthrough the second conduction path includes the step of turning on ap-channel metal oxide semiconductor field effect transistor.
 19. Themethod of claim 14, wherein the step of enabling the second conductionpath includes the steps of: decreasing the coil current to a secondlimit value to produce a charge control signal; and generating the coilcurrent through the first or second conduction path with the chargecontrol signal.